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IS61LF102436A IS61VF102436A IS61LF204818A IS61VF204818A 1M x 36, 2M x 18 36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
FEATURES
* Internalself-timedwritecycle * IndividualByteWriteControlandGlobalWrite * Clockcontrolled,registeredaddress,dataand control * BurstsequencecontrolusingMODEinput * Three chip enable option for simple depth expansion and address pipelining * Commondatainputsanddataoutputs * AutoPower-downduringdeselect * Singlecycledeselect * SnoozeMODEforreduced-powerstandby * PowerSupply LF: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VF: Vdd 2.5V + 5%, Vddq 2.5V + 5% * JEDEC100-PinTQFPand165-pinPBGApackages. * Lead-freeavailable APRIL 2008
DESCRIPTION The ISSI IS61LF/VF102436A and IS61LF/VF204818A
are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LF/ VF102436Aisorganizedas1,048,476wordsby36bits. The IS61LF/VF204818Aisorganizedas2M-wordsby18 bits. Fabricated with ISSI'sadvancedCMOStechnology, the device integrates a 2-bit burst counter, high-speed SRAMcore,andhigh-drivecapabilityoutputsintoasingle monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Writecyclesareinternallyself-timedandareinitiatedbythe risingedgeoftheclockinput.Writecyclescanbeoneto four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Bytewriteoperationisperformedbyusingbytewriteenable (BWE) input combined with one or more individual byte write signals (BWx). Inaddition,GlobalWrite(GW) is available for writing all bytes at one time, regardless of the byte write controls. BurstscanbeinitiatedwitheitherADSP (Address Status Processor)orADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. Themodepinisusedtoselecttheburstsequenceorder, LinearburstisachievedwhenthispinistiedLOW.InterleaveburstisachievedwhenthispinistiedHIGHorleft floating.
FAST ACCESS TIME
Symbol tkq tkc Parameter ClockAccessTime CycleTime Frequency -6.5 6.5 7.5 133 -7.5 7.5 8.5 117 Units ns ns MHz
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
1
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
BLOCK DIAGRAM
MODE CLK CLK Q0 A0 A0'
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1
A1'
1Mx36; 2Mx18; MEMORY ARRAY
20/21
A
20/21
D
Q
18/19
ADDRESS REGISTER
CE CLK 36, or 18 36, or 18
GW BWE BW(a-d) x18: a,b x36: a-d
DQ(a-d) BYTE WRITE REGISTERS
CLK
D
Q
CE CE2 CE2 D Q
2/4/8
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
36, or 18 DQa - DQd OE
ZZ
POWER DOWN
OE
2
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
165-PIN BGA
165-Ball,13x15mmBGA
BOTTOMvIEW
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
3
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
165 PBGA PACKAGE PIN CONFIGURATION
1M x 36 (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC A 3 CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A 4 BWc BWd Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 5 BWb BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss A A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 9 ADV ADSP Vddq Vddq Vddq Vddq Vddq Nc Vddq Vddq Vddq Vddq Vddq A A 10 A A Nc DQb DQb DQb DQb Nc dqa dqa dqa dqa A A 11 NC NC DQPb DQb DQb DQb DQb ZZ dqa dqa dqa dqa A A
NCDQPa
Note: * A0 and A1arethetwoleastsignificantbits(LSB)oftheaddressfieldandsettheinternalburstcounterifburstisdesired. (UnderEvaluation)
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 Pin Name Address Inputs SynchronousBurstAddress Inputs SynchronousBurstAddress Advance. AddressStatusProcessor Address Status Controller GlobalWriteEnable Synchronous Clock Synchronous Chip Select Symbol BWE OE ZZ MODE NC DQa-DQd DQPa-Pd Vdd Vddq
vss
Pin Name ByteWriteEnable OutputEnable PowerSleepMode BurstSequenceSelection No Connect DataInputs/Outputs DataInputs/Outputs PowerSupply
OutputPowerSupply Ground
BWx(x=a,b,c,d) SynchronousByteWrite Controls
4
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
165 PBGA PACKAGE PIN CONFIGURATION
2M x 18 (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE 2 A A NC DQb DQb DQb DQb NC NC NC NC NC NC NC A 3 CE CE2 Vddq Vddq Vddq Vddq Vddq NC Vddq Vddq Vddq Vddq Vddq A A 4 BWb NC Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 5 NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss A A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vss A A 9 ADV ADSP Vddq Vddq Vddq Vddq Vddq Nc Vddq Vddq Vddq Vddq Vddq A A 10 A A Nc NC NC NC NC Nc dqa dqa dqa dqa NC A A 11 A NC DQPa DQa DQa DQa DQa ZZ Nc Nc Nc Nc NC A A
Note: * A0 and A1arethetwoleastsignificantbits(LSB)oftheaddressfieldandsettheinternalburstcounterifburstisdesired. (UnderEvaluation)
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 BWx(x=a,b) Pin Name Address Inputs SynchronousBurstAddress Inputs SynchronousBurstAddress Advance. AddressStatusProcessor Address Status Controller GlobalWriteEnable Synchronous Clock Synchronous Chip Select SynchronousByteWrite Controls Symbol BWE OE ZZ MODE NC DQa-DQd DQPa-Pd Vdd Vddq
vss
Pin Name ByteWriteEnable OutputEnable PowerSleepMode BurstSequenceSelection No Connect DataInputs/Outputs DataInputs/Outputs PowerSupply
OutputPowerSupply Ground
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
5
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
PIN CONFIGURATION
100-Pin TQFP
A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPc
DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pinsmusttiedtothetwoLSBsofthe address bus. A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP SynchronousProcessorAddressStatus ADV SynchronousBurstAddressAdvance BWa-BWd SynchronousByteWriteEnable BWE SynchronousByteWriteEnable CE,CE2,CE2 SynchronousChipEnable CLK Synchronous Clock DQa-DQd SynchronousDataInput/Output DQPa-DQPd vss GW MODE OE Vdd Vddq ZZ ParityDataInput/Output Ground SynchronousGlobalWriteEnable BurstSequenceModeSelection OutputEnable 3.3v/2.5vPowerSupply IsolatedOutputBufferSupply: 3.3v/2.5v SnoozeEnable
MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A
1M x 36
6
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
PIN CONFIGURATION
100-Pin TQFP
A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A
A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
2M x 18
PIN DESCRIPTIONS
Synchronous Address Inputs. These pinsmusttiedtothetwoLSBsofthe address bus. A Synchronous Address Inputs Synchronous Controller Address Status ADSC ADSP SynchronousProcessorAddressStatus ADV SynchronousBurstAddressAdvance BWa-BWb SynchronousByteWriteEnable BWE SynchronousByteWriteEnable CE,CE2,CE2 SynchronousChipEnable CLK Synchronous Clock DQa-DQb SynchronousDataInput/Output A0, A1 DQPa-DQPb Vss GW MODE OE Vdd Vddq ZZ ParityDataI/O;DQPaisparityfor DQa1-8;DQPbisparityforDQb1-8 Ground SynchronousGlobalWriteEnable BurstSequenceModeSelection OutputEnable 3.3v/2.5vPowerSupply IsolatedOutputBufferSupply: 3.3v/2.5v SnoozeEnable
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
7
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
TRUTH TABLE(1-8) (3CEoption)
OPERATION DeselectCycle,Power-Down DeselectCycle,Power-Down DeselectCycle,Power-Down DeselectCycle,Power-Down DeselectCycle,Power-Down SnoozeMode,Power-Down ReadCycle,BeginBurst ReadCycle,BeginBurst WriteCycle,BeginBurst ReadCycle,BeginBurst ReadCycle,BeginBurst ReadCycle,ContinueBurst ReadCycle,ContinueBurst ReadCycle,ContinueBurst ReadCycle,ContinueBurst WriteCycle,ContinueBurst WriteCycle,ContinueBurst ReadCycle,SuspendBurst ReadCycle,SuspendBurst ReadCycle,SuspendBurst ReadCycle,SuspendBurst WriteCycle,SuspendBurst WriteCycle,SuspendBurst ADDRESS None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L X L L L L L X X H H X H X X H H X H CE2 X X H X H X L L L L L X X X X X X X X X X X X CE2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP ADSC X L L X L X H L H L X X L X L X H L H L H L H H H H X H X H H H X H H H H H X H X H H H X H ADV WRITE X X X X X X X X X X X X X X X X X L X H X H L H L H L H L H L L L L H H H H H H H H H L H L OE X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
NOTE: 1. Xmeans"Don'tCare."HmeanslogicHIGH.LmeanslogicLOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWEareLOWorGWisLOW.WRITE = H for all BWx, BWE, GWHIGH. 3. BWaenablesWRITEstoDQa'sandDQPa.BWbenablesWRITEstoDQb'sandDQPb.BWcenablesWRITEstoDQc's and DQPc.BWdenablesWRITEstoDQd'sandDQPd.BWeenablesWRITEstoDQe'sandDQPe.BWfenablesWRITEstoDQf's andDQPf.BWgenablesWRITEstoDQg'sandDQPg.BWhenablesWRITEstoDQh'sandDQPh.DQPa-DQPhareavailable onthex72version.DQPaandDQPbareavailableonthex18version. DQPa-DQPdareavailableonthex36version. 4. All inputs except OEandZZmustmeetsetupandholdtimesaroundtherisingedge(LOWtoHIGH)ofCLK. 5. Waitstatesareinsertedbysuspendingburst. 6. ForaWRITEoperationfollowingaREADoperation,OEmustbeHIGHbeforetheinputdatasetuptimeandheldHIGHduring the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSPLOWalwaysinitiatesaninternalREADattheL-HedgeofCLK.AWRITEisperformedbysettingoneormorebytewrite enable signals and BWELOWorGWLOWforthesubsequentL-HedgeofCLK.SeeWRITEtimingdiagramforclarification.
8
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TsTg Pd IOuT VIN, VOuT VIN Vdd Parameter StorageTemperature PowerDissipation OutputCurrent(perI/O) voltageRelativetovssforI/OPins voltageRelativetovssfor for Address and Control Inputs Voltage on VddSupplyRelativetovss Value -55to+150 1.6 100 -0.5tovddq + 0.5 -0.5tovdd + 0.5 -0.5to4.6 Unit C W mA V V V
Notes: 1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
9
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
OPERATING RANGE (IS61LFxxxxx)
Range Commercial Industrial Ambient Temperature 0Cto+70C -40Cto+85C VDD 3.3v5% 3.3v5% VDDq 3.3v/2.5v5% 3.3v/2.5v5%
OPERATING RANGE (IS61VFxxxxx)
Range Commercial Industrial Ambient Temperature 0Cto+70C -40Cto+85C VDD 2.5v5% 2.5v5% VDDq 2.5v5% 2.5v5%
DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)
3.3V Symbol VOh VOl VIh VIl IlI IlO Parameter OutputHIGHvoltage OutputLOWvoltage InputHIGHvoltage InputLOWvoltage Input Leakage Current OutputLeakageCurrent Test Conditions IOh = -4.0 mA (3.3V) IOh = -1.0 mA (2.5V) IOl = 8.0 mA (3.3V) IOl = 1.0 mA (2.5V) Vss VIN Vdd(1) Vss VOuT Vddq, OE = VIh Min. 2.4 -- 2.0 -0.3 -5 -5 Max. -- 0.4 Vdd + 0.3 0.8 5 5 Min. 2.0 -- 1.7 -0.3 -5 -5 2.5V Max. -- 0.4 Vdd + 0.3 0.7 5 5 Unit V V V V A A
Note: 1. VIl (min.) = -2.0V AC (pulse width 2.0 ns). Not 100% tested. VIh (max.) = Vdd +2.0V Ac (pulse width 2.0 ns). Not 100% tested.
POWER SUPPLY CHARACTERISTICS(1) (OverOperatingRange)
6.5 MAX x18 x36 360 360 375 375 295 155 160 155 160 7.5 MAX x18 x36 340 340 350 350 295 155 160 155 160
Symbol Icc
Parameter ACOperating Supply Current
Isb
StandbyCurrent TTL Input
IsbI
StandbyCurrent cMOs Input
Test Conditions Temp. range DeviceSelected, Com. OE = VIh, ZZ VIl, Ind. All Inputs 0.2V or Vdd - 0.2V, typ.(2) Cycle Time tkc min. DeviceDeselected, Com. Vdd = Max., Ind. All Inputs VIl or VIh, ZZ VIl, f=Max. DeviceDeselected, Com. Vdd = Max., Ind. VIN Vss +0.2vorVdd - 0.2V typ.(2) f=0

Unit mA
mA
140 145 80
140 145
140 145 80
140 145
mA
Note: 1. MODEpinhasaninternalpullupandshouldbetiedtovdd or Vss. It exhibits 100 A maximum leakage current when tied to Vss+0.2vor Vdd - 0.2V. 2.Typicalvaluesaremeasuredatvcc=3.3v,TA=25oC and not 100% tested.
10
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
CAPACITANCE(1,2)
Symbol cIN cOuT Parameter Input Capacitance Input/OutputCapacitance Conditions VIN = 0V VOuT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25c, f=1MHz,vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter InputPulseLevel InputRiseandFallTimes InputandOutputTiming and Reference Level OutputLoad Unit 0vto3.0v 1.5ns 1.5v SeeFigures1and2
AC TEST LOADS
317
ZO = 50 OUTPUT 50 1.5V
3.3V OUTPUT 5 pF Including jig and scope
Figure 2
351
Figure 1
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
11
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
2.5V I/O AC TEST CONDITIONS
Parameter InputPulseLevel InputRiseandFallTimes InputandOutputTiming and Reference Level OutputLoad Unit 0vto2.5v 1.5ns 1.25v SeeFigures3and4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667
ZO = 50 OUTPUT
+2.5V
OUTPUT
50
1,538
1.25V
5 pF Including jig and scope
Figure 3
Figure 4
12
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (OverOperatingRange)
Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlZ(2,3) tkqhZ(2,3) tOEq tOElZ(2,3) tOEhZ(2,3) tAs tWs tcEs tAVs tds tAh tWh tcEh tAVh tdh tPds tPus Notes: Parameter ClockFrequency CycleTime ClockHighTime ClockLowTime ClockAccessTime ClockHightoOutputInvalid ClockHightoOutputLow-Z ClockHightoOutputHigh-Z OutputEnabletoOutputvalid OutputEnabletoOutputLow-Z OutputDisabletoOutputHigh-Z AddressSetupTime Read/WriteSetupTime ChipEnableSetupTime AddressAdvanceSetupTime DataSetupTime Address Hold Time WriteHoldTime ChipEnableHoldTime AddressAdvanceHoldTime DataHoldTime ZZHightoPowerDown ZZLowtoPowerDown 6.5 Min. -- 7.5 2.2 2.2 -- 2.5 2.5 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 -- -- Max. 133 -- -- -- 6.5 -- -- 3.8 3.2 -- 3.5 -- -- -- -- -- -- -- -- -- -- 2 2 7.5 Min. Max. -- 117 8.5 -- 2.5 -- 2.5 -- -- 7.5 2.5 -- 2.5 -- -- 4.0 -- 3.4 0 -- -- 3.5 1.5 -- 1.5 -- 1.5 -- 1.5 -- 1.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- 0.5 -- -- 2 -- 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc
1. ConfigurationsignalMODEisstaticandmustnotchangeduringnormaloperation. 2. Guaranteedbutnot100%tested.Thisparameterisperiodicallysampled. 3. Tested with load in Figure 2.
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
13
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
READ/WRITE CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP is blocked by CE inactive
tSH
ADSP
tSS
ADSC
ADV
tAS tAH
Address
RD1
tWS tWH
WR1
RD2
RD3
GW
tWS tWH
BWE
tWS tWH
BWd-BWa
tCES tCEH
WR1 CE Masks ADSP
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
CE2
tCES tCEH
Unselected with CE2
CE2
tOEHZ
OE
tOEQX tKQX
High-Z tKQLZ tKQ
DATAOUT
High-Z
tKQLZ tKQ
1a
tKQX tKQHZ
2a
2b
2c
2d
tKQHZ
DATAIN
High-Z
tDS
1a
tDH
Single Read Flow-through
Single Write
Burst Read
Unselected
14
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
WRITE CYCLE TIMING
tKC
CLK
tSS tSH tKH tKL
ADSP is blocked by CE1 inactive ADSC initiate Write
ADSP ADSC ADV must be inactive for ADSP Write tAVS ADV
tAS tAH tAVH
Address
WR1
tWS tWH
WR2
WR3
GW
tWS tWH
BWE
tWS tWH tWS tWH
BWd-BWa
tCES tCEH
WR1
WR2 CE1 Masks ADSP
WR3
CE
tCES tCEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
OE High-Z
tDS tDH
DATAOUT
DATAIN
High-Z
1a
BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d
3a
Single Write
Burst Write
Write
Unselected
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
15
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Isb2 tPds tPus tZZI trZZI Parameter CurrentduringSNOOZEMODE ZZ active to input ignored ZZ inactive to input sampled ZZactivetoSNOOZEcurrent ZZinactivetoexitSNOOZEcurrent Conditions ZZ Vih Min. -- -- 2 -- 0 typ. (1) 27 Max. 90 2 -- 2 -- Unit mA cycle cycle cycle ns
1.Typicalvaluesaremeasuredatvcc=3.3v,TA=25oC and not 100% tested.
SNOOZE MODE TIMING
CLK
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
16
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
ORDERING INFORMATION (VDD = 3.3V/VDDq = 2.5V/3.3V) Commercial Range: 0C to +70C
Configuration 1Mx36 2Mx18 Access Time 6.5 6.5 Order Part Number IS61LF102436A-6.5TQL IS61LF102436A-6.5B3 IS61LF204818A-6.5TQ IS61LF204818A-6.5TQL IS61LF204818A-6.5B3 Package 100TQFP,Lead-free 165PBGA 100TQFP 100TQFP,Lead-free 165PBGA
Industrial Range: -40C to +85C
Configuration 1Mx36 1Mx36 2Mx18 2Mx18 Access Time 6.5 7.5 6.5 7.5 Order Part Number IS61LF102436A-6.5TQLI IS61LF102436A-6.5B3I IS61LF102436A-7.5TQI IS61LF102436A-7.5TQLI IS61LF102436A-7.5B3I IS61LF102436A-7.5B3LI IS61LF204818A-6.5TQI IS61LF204818A-6.5B3I IS61LF204818A-7.5TQI IS61LF204818A-7.5TQLI IS61LF204818A-7.5B3I Package 100TQFP,Lead-free 165PBGA 100TQFP 100TQFP,Lead-free 165PBGA 165PBGA,Lead-free 100TQFP 165PBGA 100TQFP 100TQFP,Lead-free 165PBGA

Integrated Silicon Solution, Inc.
Rev. B 04/17/08
17
IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A
ORDERING INFORMATION (VDD = 2.5V /VDDq = 2.5V) Commercial Range: 0C to +70C
Configuration 1Mx36 1Mx36 2Mx18 2Mx18 Access Time 6.5 7.5 6.5 7.5 Order Part Number IS61vF102436A-6.5TQ IS61vF102436A-6.5B3 IS61vF102436A-7.5TQ IS61vF102436A-7.5B3 IS61vF204818A-6.5TQ IS61vF204818A-6.5B3 IS61vF204818A-7.5TQ IS61vF204818A-7.5B3 Package 100TQFP 165PBGA 100TQFP 165PBGA 100TQFP 165PBGA 100TQFP 165PBGA

Industrial Range: -40C to +85C
Configuration 1Mx36 1Mx36 2Mx18 2Mx18 Access Time 6.5 7.5 6.5 7.5 Order Part Number IS61vF102436A-6.5TQI IS61vF102436A-6.5B3I IS61vF102436A-7.5TQI IS61vF102436A-7.5TQLI IS61vF102436A-7.5B3I IS61vF204818A-6.5TQI IS61vF204818A-6.5B3I IS61vF204818A-7.5TQI IS61vF204818A-7.5B3I Package 100TQFP 165PBGA 100TQFP 100TQFP,Lead-free 165PBGA 100TQFP 165PBGA 100TQFP 165PBGA

18
Integrated Silicon Solution, Inc.
Rev. B 04/17/08
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package) Package Code: TQ
D D1
E
E1
N
1
C e SEATING PLANE
L1 L
A2 A1 b
A
Symbol Ref. Std. No. Leads (N) 100 A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o
Millimeters Min Max
Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o
Inches Min Max
-- 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o
Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PK13197LQ Rev. D 05/08/03
PACKAGING INFORMATION
Ball Grid Array Package Code: B (165-pin)
TOP VIEW
A1 CORNER 1
A B C D E F G H J K L M N P R
b (165X)
BOTTOM VIEW
A1 CORNER 9 8 7 6 5 4 3 2 1
A B C D
2
3
4
5
6
7
8
9
10
11
11 10
e
E F G
D D1
H J K L M N P R
E1 E A2 A1 A
e
BGA - 13mm x 15mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.25 -- 14.90 13.90 12.90 9.90 -- 0.40
INCHES Min. Nom. Max.
165
Notes: 1. Controlling dimensions are in millimeters.
Min.
Nom. Max.
165 -- 0.33 0.79 15.00 14.00 13.00 10.00 1.20 0.40 -- 15.10 14.10 13.10 10.10 -- 0.50
-- 0.010 -- 0.587 0.547 0.508 0.390 -- 0.016
-- 0.031 0.591 0.551 0.512 0.394 0.039 0.018
0.047 -- 0.594 0.555 0.516 0.398 -- 0.020
0.013 0.016
1.00
0.45
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 06/11/03

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